The write output interface of a data processing channel usually is ideally intended to comply with two basic criteria, which are highest possible speed and highest possible robustness against electrostatic discharge (ESD) events. Meeting both criteria at the same time is a difficult task for e.g. the following reasons. On the one hand, in order to achieve a high speed, reduction of capacitances at the write interface is desired. On the other hand, in order to achieve a high robustness against ESD events, large protection structures are commonly used, which add to the capacitance at the write pins. In the following description, the terms “write pin”, “output pin” or just “pin” are used interchangeably and are understood to mean an output pin or write pin of a write driver circuit.
Besides the afore-mentioned basic criteria, a write driver may have to fulfill certain specifications for the signal swing, which is commonly very large to cope e.g. with losses on the driven lines or to provide sufficient input swing for connected input stages to operate properly. Often, the desired high-swing is complemented by a need for a large common-mode voltage at the write pins. As an example, a typical differential signal swing may be about 600 mV peak-to-peak at a common-mode voltage of, for example, 2.5 V.
In modern deep sub-micron CMOS processes (complementary metal oxide semiconductor) the maximum voltages that the highest speed core devices can handle may often be limited because these devices are commonly build with the thinnest available gate-oxide thickness. For example, in a 130-nm process, core devices may typically handle voltages up to about 1.5 V, in a 90-nm process, core devices may, for example, handle voltages up to about 1.3 V, and in a 65-nm process, core devices may, for example, handle voltages up to about 1.1 V. Such low maximum voltages may cause problems when high common-mode voltages are used, in particular common-mode voltages that are higher than the maximum voltages that can be handled by the core devices. In this case, special circuits may have to be developed to allow an operation of low-voltage devices at a high common-mode voltage.
Another property of low-voltage devices is that they are usually not very robust with respect to ESD discharge voltages. Hence, special measures to limit ESD voltages to the maximum tolerated levels may be implemented. Furthermore, in typical differential write interfaces, a direct pin-to-pin ESD discharge event may be possible which may apply even stronger stress conditions to the devices that connect to the pins.